DSC POWER 864 - REV2 Especificaciones Pagina 32

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 254
  • Tabla de contenidos
  • MARCADORES
  • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 31
PIC24F16KA102 FAMILY
DS39927B-page 30 Preliminary © 2009 Microchip Technology Inc.
TABLE 4-4: ICN REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CNEN1 0060 CN15IE
(1)
CN14IE CN13IE CN12IE CN11IE
CN9IE CN8IE CN7IE
(1)
CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062
CN30IE CN29IE CN27IE
(1)
CN24IE
(1)
CN23IE CN22IE CN21IE —CN16IE
(1)
0000
CNPU1 0068 CN15PUE
(1)
CN14PUE CN13PUE CN12PUE CN11PUE CN9PUE CN8PUE CN7PUE
(1)
CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A
CN30PUE CN29PUE —CN27PUE
(1)
—CN24PUE
(1)
CN23PUE CN22PUE CN21PUE CN16PUE
(1)
0000
CNPD1 0070 CN15PDE
(1)
CN14PDE CN13PDE CN12PDE CN11PDE CN9PDE CN8PDE CN7PDE
(1)
CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE 0000
CNPD2 0072
CN30PDE CN29PDE —CN27PDE
(1)
—CN24PDE
(1)
CN23PDE CN22PDE CN21PDE CN16PDE
(1)
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are not implemented in 20-pin devices.
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
INTCON1 0080 NSTDIS
MATHERR ADDRERR STKERR OSCFAIL 0000
INTCON2 0082 ALTIVT DISI
INT2EP INT1EP INT0EP 0000
IFS0 0084 NVMIF
AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0086 U2TXIF U2RXIF INT2IF
INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS3 008A
—RTCIF 0000
IFS4 008C
—CTMUIF —HLVDIF CRCIF U2ERIF U1ERIF 0000
IEC0 0094 NVMIE
AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0096 U2TXIE U2RXIE INT2IE
INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC3 009A
—RTCIE 0000
IEC4 009C
—CTMUIE —HLVDIE CRCIE U2ERIE U1ERIE 0000
IPC0 00A4
T1IP2 T1IP1 T1IP0 OC1IP2 OC1IP1 OC1IP0 IC1IP2 IC1IP1 IC1IP0 INT0IP2 INT0IP1 INT0IP0 4444
IPC1 00A6
T2IP2 T2IP1 T2IP0 4444
IPC2 00A8
U1RXIP2 U1RXIP1 U1RXIP0 SPI1IP2 SPI1IP1 SPI1IP0 SPF1IP2 SPF1IP1 SPF1IP0 —T3IP2T3IP1T3IP04444
IPC3 00AA
NVMIP2 NVMIP1 NVMIP0 AD1IP2 AD1IP1 AD1IP0 U1TXIP2 U1TXIP1 U1TXIP0 4044
IPC4 00AC
CNIP2 CNIP1 CNIP0 CMIP2 CMIP1 CMIP0 MI2C1P2 MI2C1P1 MI2C1P0 SI2C1P2 SI2C1P1 SI2C1P0 4444
IPC5 00AE
INT1IP2 INT1IP1 INT1IP0 0004
IPC7 00B2
U2TXIP2 U2TXIP1 U2TXIP0 U2RXIP2 U2RXIP1 U2RXIP0 INT2IP2 INT2IP1 INT2IP0 4440
IPC15 00C2
RTCIP2 RTCIP1 RTCIP0 0400
IPC16 00C4
CRCIP2 CRCIP1 CRCIP0 U2ERIP2 U2ERIP1 U2ERIP0 U1ERIP2 U1ERIP1 U1ERIP0 4440
IPC18 00C8
HLVDIP2 HLVDIP1 HLVDIP0 0004
IPC19 00CA
CTMUIP2 CTMUIP1 CTMUIP0 0040
INTTREG 00E0 CPUIRQ
—VHOLD ILR3 ILR2 ILR1 ILR0 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Vista de pagina 31
1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 253 254

Comentarios a estos manuales

Sin comentarios